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W631GG6KB
Notes:
1. All DDR3 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE# and CKE at the rising edge of the clock.
The MSB of BA, RA and CA are device density and configuration dependant.
2. RESET# is Low enable command which will be used only for asynchronous reset so must be maintained HIGH during any
function.
3. Bank addresses (BA) determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
4. ― V ‖ means ― H or L (but a defined logic level) ‖ and ― X ‖ means either ― defined or undefined (like floating) logic level ‖ .
5. Burst reads or writes cannot be terminated or interrupted and Fixed/on-the-fly BL will be defined by MRS.
6. The Power Down Mode does not perform any refresh operation.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
8. Self Refresh Exit is asynchronous.
9. V REF (Both V REFDQ and V REFCA ) must be maintained during Self Refresh operation. V REFDQ supply may be turned OFF
and V REFDQ may take any value between V SS and V DD during Self Refresh operation, provided that V REFDQ is valid and
stable prior to CKE going back High and that first Write operation or first Write Leveling Activity may not occur earlier than
512 nCK after exit from Self Refresh.
10. The No Operation command should be used in cases when the DDR3 SDRAM is in an idle or wait state. The purpose of the
No Operation command (NOP) is to prevent the DDR3 SDRAM from registering any unwanted commands between
operations. A No Operation command will not terminate a pervious operation that is still executing, such as a burst read or
write cycle.
11. The Deselect command performs the same function as No Operation command.
12. Refer to the CKE Truth Table for more detail with CKE transition.
Publication Release Date: Dec. 09, 2013
Revision A05
- 95 -
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